The present invention relates to a semiconductor device fabricating method for fabricating a semiconductor device of complementary MIS (Metal Insulation Semiconductor) type having compression strain induced in the channel of the p-transistor.
In semiconductor devices, for high achievements, as of speedy operation, low power consumption and high integration, etc., the minimum processing dimension has been increasingly nanonized. In the generation of the minimum processing dimensions of below 65 nm including 65 nm, the nanonization is technologically very difficult, and the higher achievements resorting to the nanonization alone are being limited.
Here, as a high achievement transistor which does not resort to the nanonization is noted the so-called strained silicon transistor having strain induced in the silicon single crystal of the channel of the MIS or MOS transistor. In the strained silicon transistor, an Si single crystal film is formed on an SiGe film whose lattice constant is larger than that of the Si single crystal, whereby the electron mobility of the Si single crystal film can be improved. The n-transistor using such strained Si single crystal film as the channel to thereby improve the operation speed is proposed.
The hole mobility (1900 cm2/(V*s)) in the usual Si single crystal is lower than the electron mobility (3900 cm2/(V*s)). In the complementary semiconductor device including a p-transistor and an n-transistor, the operation speed of the p-transistor is lower, which makes low the operation speed of the semiconductor device as a whole. Furthermore, even when the operation speed of the n-transistor by using a strained silicon substrate, the operation speed of the semiconductor device as a whole cannot be achieved, but the cost increase, etc. by the use of the strained silicon substrate are problems.
To improve the operation speed of the p-transistor, as illustrated in FIG. 1, a semiconductor device including an SiGe film 101, 102 in the source/drain regions of the p-transistor to thereby apply compressive strain to the channel (Si single crystal) 104 below the gate oxide film 103 by the SiGe films 101, 102 to improve the hole mobility is proposed (refer to Patent Reference 1). Patent Reference 1 is U.S. Pat. No. 6,621,131.
In Patent Reference 1, impurity diffused regions each formed of a shallow junction region 105 and a deep junction region 106 of a p-transistor are formed, then trenches 101a, 102a are formed in the source/drain regions, and the SiGe film 101, 102 is formed on the surfaces of the trenches 101a, 102a by thermal CVD.
However, when the SiGe film 101, 102 is formed after the impurity diffused regions have been formed, the thermal processing is performed up to about 740 C, which diffuses the impurity, and short channel effect takes place. Especially, the transistor whose gate length is below 100 nm including 100 nm has the problem that the roll off characteristics of the threshold voltage is deteriorated.
Patent Reference 1 does not disclose a specific method for fabricating a complementary semiconductor device including a p-transistor and an n-transistor.